Description
Explore how a 3-to-8 decoder works in digital circuits. Learn its truth table, Verilog implementation, testbench, and real-time simulation output.
Introduction
A decoder is a crucial component in digital logic design. It takes binary input and activates one specific output line. In microprocessors, memory systems, and embedded controllers, decoders are used for address decoding and control signal routing. This blog explains the 3-to-8 decoder using Verilog with simulation results.
Concept Explanation
A decoder converts binary inputs into a one-hot output, meaning only one output line is active (logic high) for each input combination. A 3-to-8 decoder has 3 input bits and 8 output lines, enabling it to represent 8 distinct states.
Inputs: a2, a1, a0
Outputs: d0 to d7
Truth Table
a2 | a1 | a0 | d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Verilog Implementation
// Pantech e-learning
// 3 to 8 decoder implementation using behavioural modelling
module decoder(
input [2:0] a,
output reg [7:0] d
);
always @(*) begin
d = 8’b00000000;
d[a] = 1’b1;
end
endmodule
Testbench Code
// Pantech e-learning
module tb;
reg [2:0] a;
wire [7:0] d;
decoder uut(.a(a), .d(d));
initial begin
a = 0;
repeat (8) begin
#10;
$display(“a = %b d = %b”, a, d);
a = a + 1;
end
$finish;
end
endmodule
Output
The simulation output will sequentially display the 8-bit one-hot output for each input from 000 to 111, verifying correct decoder operation.
Figure 1: 3 to 8 decoder simulation output log file
Figure 2: 3 too 8 decoder simulation output waveform
Top 5 FAQs on Decoders
Q1: What is the purpose of a decoder?
A decoder activates a specific output line based on binary input. It is used in memory, microprocessors, and digital displays.
Q2: How many outputs does a 3-to-8 decoder have?
A 3-to-8 decoder has 8 outputs (2³ = 8), one for each possible input combination.
Q3: Can multiple outputs be high at the same time in a decoder?
No, in a standard decoder, only one output is high at any time, based on the input.
Q4: What happens if inputs are undefined (X or Z)?
Decoder outputs can behave unpredictably if inputs are undefined. Proper initialization is important.
Q5: What is the difference between an encoder and a decoder?
A decoder converts binary input into one-hot output, while an encoder does the reverse—it converts one-hot input into binary.
Conclusion
You’ve learned how a 3-to-8 decoder works and how to implement it in Verilog using behavioral modelling. Understanding decoders is fundamental for applications in memory selection, instruction decoding, and digital displays.
Try It Yourself
Run the 3-to-8 Decoder Verilog simulation online:
Click here to simulate on EDA Playground
Call to Action
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A. Manikandan is an RTL Engineer at Pantech India Solutions Pvt. Ltd. With a strong passion for digital design ,FPGAs and ASIC bus protocols. he specializes in FPGA and hardware development, sharing insights to bridge the gap between academia and industry.
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